Non-volatile memory devices are used in a number of applications, whenever data must be retained even if a power supply is off. Flash memories are a particular type of non-volatile memory device, in which each cell can be electrically programmed, but a large number of cells (which form a sector) must be erased at the same time. Typically, each cell is formed by a floating gate MOS transistor that stores a logic level defined by its threshold voltage (which depends on the electric charge stored in the corresponding floating gate). In particular, in a flash memory device with NAND architecture the cells are arranged in strings, each one consisting of a set of cells connected in series. An advantage of this architecture is the reduced area occupation (essentially due to the low number of electrical contacts and to the small size of the cells). This makes the NAND memory devices particularly advantageous in a number of applications (for example, for memory cards).
In order to further reduce the complexity of the NAND memory devices, the cells of a selected sector are generally erased by applying a single blind erasing pulse, which is dimensioned so as to lower their threshold voltages below a reference reading voltage (typically, 0V). Moreover, the NAND memory devices implement a decoding system that is able to bias the various cells selectively with positive voltages only (i.e., equal or higher than zero).
A problem of the NAND memory devices is due to the capacitive coupling between the floating gates of adjacent cells; such effect may make the threshold voltage of each cell dependent on the electric charge stored in the floating gates of the adjacent cells.
The capacitive coupling effect modifies the threshold voltage of each cell whenever the adjacent cells are programmed. The suffered variation increases with the increment of the threshold voltages of the adjacent cells during the programming operation. Thus, the problem is particularly serious when the adjacent cells to be programmed start from very low threshold voltages. As a result, this variation may cause errors during the reading operations.
In order to limit the capacitive coupling effect, it would be desirable to increase the threshold voltages of the erased cells; for example, it is possible to shift the threshold voltages of the erased cells by applying a soft programming pulse (of reduced amplitude and duration). However, after this operation it is necessary to verify that the cells are still erased. For this purpose, the cells should be read with respect to the reading voltage with a negative margin (so as to ensure that they are not approaching the reading voltage beyond a safety limit).
The above-described operation requires the biasing of the cells to be read with a negative voltage (so as to make it possible to discriminate whether their threshold voltages are actually lower than the desired value). Therefore, this operation is inherently incompatible with the structure of the NAND memory devices known in the art (wherein only a positive decoding system is available).